Flash Memory Specifications Archive

Last updated - 2018/04/09

Micron

3D NAND - 1st generation

Micron 3D NAND Datasheet

I found this table interesting enough that I wanted to highlight it. Micron seem to manufacture the chips in a way that the page size remains the standard 16KiB but the erase block is a multiple of three (above should read 24MiB + 2208KiB). The 2208KiB is simply where the error correction information is stored. Unfortunately, there is no information about the number of expected erase cycles.

Anandtech also shares the following details about Micron's 3D NAND: 

On a smaller scale, the 3D NAND will have a page size of 16kB and erase block sizes of 16MiB for the MLC and 24MiB for the TLC. Because CPUs and file systems are still mostly dealing with 4KiB chunks, Micron has included a partial page read capability that allows for a 4KiB read to be done a bit faster and with about half the power of a full 16KiB page read.

This is an interesting data point, one which we can take a look at with programs like "flashbench". Sometimes one can spot half page reads (8KiB) being faster but optimizing for file system page size is even better.

SK Hynix

I haven't managed to find much information about Hynix chips but they did a presentation in 2022, where they detailed the upcoming 300 layer NAND flash chips.

While most of the information is not really interesting, they do state that page size has now moved up to 16KiB, which has implications for operating system performance. Sadly, there is no information available about block sizes. This is still TLC type NAND.

Hynix QLC 96L NAND was using 24MiB erase blocks in 2020, but this is TLC, still I don't expect to be smaller than that.

Toshiba

BiCS 3 QLC (3D NAND)

Details are very scarce about these chips, except that dies are available in 768Gb capacities and that endurance of this solution is confirmed to be around 1000 erase cycles (Toshiba QLC NAND - Anandtech).

BiCS 4

Not much information is available, except that it features 96 layers.